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RxFIFO fills, it bids with a progressively higher priority for interrupt
service. Similarly, as empty space in a transmitter s TxFIFO Enabling and Activating Interrupt sources
increases, its interrupt arbitration priority increases. An interrupt source becomes enabled when its interrupt capability is
set by writing to the Interrupt Mask Register, IMR. An interrupt
source can never generate an IRQN or have its bid or interrupt
IACKN Cycle, Update CIR
number appear in the CIR unless the source has been enabled by
When the host CPU responds to the interrupt, it will usually assert
the appropriate bit in an IMR.
the IACKN signal low. This will cause the OCTART to generate an
IACKN cycle in which the condition of the interrupting device is
An interrupt source is active if it is presenting its bid to the interrupt
determined. When IACKN asserts, the last valid interrupt number is
arbiter for evaluation. Most sources have simple activation
captured in the CIR. The value captured presents most of the
requirements. The watch-dog timer, break received, Xon/Xoff or
important details of the highest priority interrupt at the moment the
Address Recognition and change of state interrupts become active
IACKN (or the Update CIR command) was asserted.
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
The Octal UART will respond to the IACKN cycle with an interrupt
ICR (Interrupt Control Register).
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or ,when Interrupt Vector Modification is
The transmitter and receiver functions have additional controls to
enabled via ICR, it may contain codes for the interrupt type and/or
modify the condition upon which the initiation of interrupt bidding
interrupting channel. This allows the interrupt vector to steer the
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
interrupt service directly to the proper service routine. The interrupt
These fields can be used to start bidding or arbitration when the
value captured in the CIR remains until another IACKN cycle occurs
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
or until an Update CIR command is given to the OCTART. The
transmitter it is not full, 50% empty, 75% empty and empty.
interrupting channel and interrupt type fields of the CIR set the
current interrupt context of the OCTART. The channel component
Example: To increase the probability of transferring the contents of a
of the interrupt context allows the use of Global Interrupt Information
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
registers that appear at fixed positions in the register address map.
full. This will prevent its relatively high priority from winning the
For example, a read of the Global RxFIFO will read the channel B
arbitration process at low fill levels. A high threshold level could
RxFIFO if the CIR interrupt context is channel b receiver. At another
accomplish the same thing, but may also mask out low priority
time read of the GRxFIFO may read the channel D RxFIFO (CIR
interrupt sources that must be serviced. Note that for fast channels
holds a channel D receiver interrupt) and so on. Global registers
and/or long interrupt latency times using this feature should be used
exist to facilitate qualifying the interrupt parameters and for writing to
with caution since it reduces the time the host CPU has to respond
and reading from FIFOs without explicitly addressing them.
to the interrupt request before receiver overrun occurs.
The CIR will load with x 00 if IACKN or Update CIR is asserted when
Setting Interrupt Priorities
the arbitration circuit is NOT asserting and interrupt. In this
The bid or interrupt number presented to the interrupt arbiter is
condition there is no arbitration value that exceeds the threshold
composed of character counts, channel codes, fixed and
value.
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in the table below: The value
Polling
represented by the bits 9 to 3 in the table below are compared
Many users prefer polled to interrupt driven service where there are
against the value represented by the Threshold. The Threshold
a large number of fast data channels and/or the host CPU s other
,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such
interrupt overhead is low. The Octal UART is functional in this
that bit 6 of the threshold is compared to bit 9 of the interrupt value
environment.
generated by any of the sources. When ever the value of the
interrupt source is greater than the threshold the interrupt will be
The most efficient method of polling is the use of the update CIR
generated.
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
The channel number arbitrates only against other channels. The
capture function that an IACKN falling edge would accomplish in an
threshold is not used for the channel arbitration. This results in
interrupt driven system. A subsequent read of the CIR, at the same
channel D having the highest arbitration number. The decreasing
address, will give information about an interrupt, if any. If the CIR
order is H to A. If all other parts of an arbitration are equal then the
contains 0s, no interrupt is awaiting service. If the value is
channel number will determine which channel will dominate in the
non zero, the fields of the CIR may be decoded for type, channel
arbitration process
and character count information. Optionally, the global interrupt
registers may be read for particular information about the interrupt .
1999 Jan 14 13
Philips Semiconductors Product specification
Octal UART for 3.3V and 5V supply voltage SC28L198
Table 1. Interrupt Arbitration Priority
Type B9 B8 B7 B6 B5 B4 B3 Bits 2:0
Receiver w/o error RxFIFO Byte Count 1 0 0 1 Channel No
Receiver w/ error RxFIFO Byte Count 1 1 0 1 Channel No
Transmitter 0 TxFIFO Byte Count 1 0 0 Channel No
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